The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Mar. 01, 2012
Applicants:

Igor Tselniker, Haifa, IL;

Netta Sigron, Haifa, IL;

Moshe Nazarathy, Haifa, IL;

Inventors:

Igor Tselniker, Haifa, IL;

Netta Sigron, Haifa, IL;

Moshe Nazarathy, Haifa, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/61 (2013.01); H04L 25/03 (2006.01); H04L 27/00 (2006.01); H04L 27/233 (2006.01); H04L 27/38 (2006.01);
U.S. Cl.
CPC ...
H04B 10/6165 (2013.01); H04L 25/03019 (2013.01); H04L 27/0014 (2013.01); H04L 27/2331 (2013.01); H04L 27/38 (2013.01); H04L 2027/0024 (2013.01);
Abstract

A receiver and a multi-symbol-differential-detection (MSDD) module, the MSDD may include an input node for receiving an input signal having a noisy phase; a summation and rotation unit; and an output unit; wherein the output unit is arranged to output an output signal and a normalized output signal; wherein the output signal represents the input signal but has a reconstructed phase; wherein the summation and rotation unit is arranged to receive the input signal and the output signal and to provide a reference signal that reflects a weighted sum of phase rotated and delayed previously received input signals; wherein the output unit comprises a phase difference calculator, a slicer, a delay unit and a normalizer; wherein the phase difference calculator is arranged to generate a difference signal indicative of a phase difference between the reference signal and the input signal; wherein the slicer and the delay unit are arranged to generate the output signal by slicing the difference signal to provide a sliced signal and by delaying the sliced signal; and wherein the normalizer is arranged to normalize the output signal to provide the normalized output signal.


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