The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Jan. 20, 2012
Applicants:

Shigehiro Takashima, Tokorozawa, JP;

Mitsuo Akashi, Fujisawa, JP;

Yoshikazu Era, Yokohama, JP;

Atsushi Takai, Koganei, JP;

Inventors:

Shigehiro Takashima, Tokorozawa, JP;

Mitsuo Akashi, Fujisawa, JP;

Yoshikazu Era, Yokohama, JP;

Atsushi Takai, Koganei, JP;

Assignee:

Oclaro Japan, Inc., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/00 (2013.01); H04B 10/60 (2013.01); H04B 10/69 (2013.01); H04B 10/61 (2013.01);
U.S. Cl.
CPC ...
H04B 10/613 (2013.01); H04B 10/69 (2013.01);
Abstract

In pattern synchronization for correctly regenerating received data, which is performed in an optical receiver for receiving an optical signal that has been subjected to quadrature phase modulation, signal conduction is quickly established without using duplicate combinations of bit shifting and pattern changing. A control method that does not involve verifying the duplicate combinations generated in modulation formats and pattern synchronization search orders. Specifically, a signal check circuit () performs data verification of data multiplexed by a MUX circuit () for multiplexing two data strings, and a bit shift pattern change control circuit () controls a bit shift circuit () and a pattern changing circuit () based on a result of the data verification and detects a correct combination of correct regenerated data to establish the signal conduction. At this time, for the bit shift circuit () and the pattern changing circuit (), the duplicate combinations are not verified.


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