The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Apr. 28, 2014
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Atsushi Matsuda, Akishima, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/095 (2006.01); H03L 7/091 (2006.01); H03L 7/093 (2006.01); H03L 7/07 (2006.01); H03L 7/14 (2006.01);
U.S. Cl.
CPC ...
H03L 7/095 (2013.01); H03L 7/091 (2013.01); H03L 7/093 (2013.01); H03J 2200/10 (2013.01); H03L 7/07 (2013.01); H03L 7/146 (2013.01); H03L 2207/50 (2013.01);
Abstract

An ADPLL includes a digital controlled oscillator, a first counter counting a number of clocks from the digital controlled oscillator, a second counter to count a multiplication number representing a number of the clocks in a reference clock, a TDC detecting a delayed amount of a phase of the clocks against a phase of the reference clock, an adder adding the delayed amount to a difference between the multiplication number and the number of clocks, a slew rate setting part setting a slew rate of the clocks, an ADC receiving the clocks to which the slew rate is set, a switching part switching between an output of the adder and an output of the ADC, and a controller controlling the slew rate by shifting a phase of the clocks to set a slew rate while the ADLL is locked by utilizing the TDC.


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