The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Aug. 23, 2013
Applicant:

Dialog Semiconductor B.v., 's-Hertogenbosch, NL;

Inventor:

Michail Papamichail, Den Bosch, NL;

Assignee:

Dialog Semiconductor B.V., 's-Hertogenbosch, NL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01); H03F 3/16 (2006.01); G05F 3/24 (2006.01); H03F 1/22 (2006.01); H03F 1/30 (2006.01);
U.S. Cl.
CPC ...
H03F 3/16 (2013.01); G05F 3/24 (2013.01); H03F 1/223 (2013.01); H03F 1/301 (2013.01); H03F 2200/18 (2013.01); H03F 2200/447 (2013.01); H03F 2200/456 (2013.01);
Abstract

An electronic biasing circuit provides a DC bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor. A gate of the first transistor is connected to a gate of the second transistor and supplies the DC bias voltage. A source of the first transistor is connected to a supply reference voltage. A source of the second transistor is connected to the supply reference voltage via a resistor element. The currents flowing through the first and second transistor are forced to be equal. A third transistor is connected in series with the first transistor and a fourth transistor is connected in series with the second transistor. Currents flowing through the third and fourth transistors are forced to be equal.


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