The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Dec. 23, 2011
Applicants:

Christiaan J. Werkhoven, Gilbert, AZ (US);

Chantal Arena, Mesa, AZ (US);

Inventors:

Christiaan J. Werkhoven, Gilbert, AZ (US);

Chantal Arena, Mesa, AZ (US);

Assignee:

SOITEC, Bernin, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/64 (2010.01); H01L 21/683 (2006.01); H01L 29/20 (2006.01); H01L 33/40 (2010.01);
U.S. Cl.
CPC ...
H01L 33/641 (2013.01); H01L 21/6835 (2013.01); H01L 29/2003 (2013.01); H01L 33/40 (2013.01); H01L 2924/0002 (2013.01); H01L 2933/0075 (2013.01);
Abstract

Methods for fabricating a semiconductor substrate include forming a first substrate layer over a surface of a first semiconductor layer, and thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer may be formulated to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. Semiconductor structures are fabricated using such methods.


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