The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Jan. 17, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Tea-Kwang Yu, Gyeonggi-do, KR;

Kwang-Tae Kim, Gyeonggi-do, KR;

Yong-Tae Kim, Gyeonggi-do, KR;

Bo-Young Seo, Gyeonggi-do, KR;

Yong-Kyu Lee, Gyeonggi-do, KR;

Hee-Seog Jeon, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/788 (2006.01); G11C 16/04 (2006.01); H01L 29/10 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); G11C 16/0425 (2013.01); G11C 16/0441 (2013.01); H01L 27/11529 (2013.01); H01L 29/1083 (2013.01); H01L 29/1087 (2013.01); H01L 29/7885 (2013.01);
Abstract

A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.


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