The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Mar. 04, 2014
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventors:

Yuki Fukui, Kawasaki, JP;

Hiroaki Katou, Kawasaki, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7788 (2013.01); H01L 27/088 (2013.01); H01L 29/1095 (2013.01); H01L 29/66734 (2013.01); H01L 29/7397 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01); H01L 21/823487 (2013.01); H01L 27/0922 (2013.01); H01L 29/41741 (2013.01); H01L 29/42372 (2013.01); H01L 29/78 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes forming a recess over a surface of an n-type semiconductor substrate, forming a gate insulation film over an inner wall and a bottom face of the recess, embedding a gate electrode into the recess, forming a p-type base layer in the surface layer of the substrate so as to be shallower than the recess; and forming an n-type source layer in the p-type base layer so as to be shallower than the p-type base layer. The impurity profile of the p-type base layer in a thickness direction includes a second peak being located closer to a bottom face side of the substrate than the first peak and being higher than the first peak, and a third peak located between the first peak and the second peak by implanting impurity ions three times or more at ion implantation energies different from each other.


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