The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Oct. 18, 2012
Applicant:

Panasonic Corporation, Osaka, JP;

Inventors:

Hiromitsu Takashita, Osaka, JP;

Tsuyoshi Takeda, Osaka, JP;

Keiko Kashihara, Osaka, JP;

Hiroaki Fujiwara, Nara, JP;

Shingo Yoshioka, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/768 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3114 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/03 (2013.01); H01L 24/96 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/0236 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/033 (2013.01); H01L 2224/0347 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/1411 (2013.01); H01L 2224/19 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/2105 (2013.01); H01L 2224/96 (2013.01); H01L 2924/0001 (2013.01);
Abstract

One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching the surfaces of electrodes of the semiconductor element and a circuit groove having a desired shape and a desired depth, a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion, a film-separating step of separating the resin film from the covering insulating layer, and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated.


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