The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Sep. 23, 2013
Applicant:

Anvil Semiconductors Limited, Warwickshire, GB;

Inventor:

Peter Ward, Cambridgeshire, GB;

Assignee:

Anvil Semiconductors Limited, Warwickshire, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 29/739 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 29/74 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7393 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02447 (2013.01); H01L 21/02529 (2013.01); H01L 21/02642 (2013.01); H01L 21/02645 (2013.01); H01L 29/045 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/66363 (2013.01); H01L 29/7395 (2013.01); H01L 29/74 (2013.01);
Abstract

A bipolar power semiconductor transistor is disclosed. The transistor includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type disposed on the semiconductor substrate; a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the first semiconductor region, a body region of the first conductivity type located within the semiconductor drift region, a source region of the second conductivity type located within the body region, a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region. The semiconductor substrate includes a material having silicon (Si) and the first semiconductor region includes a material having 3-step cubic silicon carbide (3C-SiC).


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