The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Mar. 25, 2013
Applicant:

Raytheon Company, Waltham, MA (US);

Inventors:

Adrian D. Williams, Methuen, MA (US);

Paul M. Alcorn, Groton, MA (US);

Assignee:

RAYTHEON COMPANY, Waltham, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 29/812 (2006.01); H01L 21/8252 (2006.01); H01L 29/778 (2006.01); H01L 27/06 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31144 (2013.01); H01L 21/8252 (2013.01); H01L 27/0605 (2013.01); H01L 29/66462 (2013.01); H01L 29/66863 (2013.01); H01L 29/7786 (2013.01); H01L 29/812 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 27/0629 (2013.01); H01L 29/2003 (2013.01);
Abstract

A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.


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