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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9082635 B1

PDFFull Text
Date of Patent:
Jul. 14, 2015

Filed:

May. 11, 2011

Wiring method, structure having wiring provided on surface, semiconductor device, wiring board, memory card, electric device, module and multilayer circuit board

Applicants:

Shingo Yoshioka, Osaka, JP;

Hiroaki Fujiwara, Nara, JP;

Hiromitsu Takashita, Osaka, JP;

Tsuyoshi Takeda, Osaka, JP;

Yuko Konno, Tokyo, JP;

Inventors:

Shingo Yoshioka, Osaka, JP;

Hiroaki Fujiwara, Nara, JP;

Hiromitsu Takashita, Osaka, JP;

Tsuyoshi Takeda, Osaka, JP;

Yuko Konno, Tokyo, JP;

Assignee:

PANASONIC CORPORATION, Osaka, JP;

Attorney:

McDermott Will & Emery LLP

Primary Examiner:

Hoa C Nguyen

Int. Cl.
CPC ...
H05K 1/11 (2006.01); H01L 25/065 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H05K 3/18 (2006.01); H01L 25/00 (2006.01); H05K 1/18 (2006.01); C23C 18/16 (2006.01); C23C 18/18 (2006.01); H01L 23/31 (2006.01); H05K 3/28 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); C23C 18/1608 (2013.01); C23C 18/1653 (2013.01); C23C 18/1893 (2013.01); H01L 21/4832 (2013.01); H01L 21/6835 (2013.01); H01L 23/49541 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/82 (2013.01); H01L 25/50 (2013.01); H05K 1/185 (2013.01); H05K 3/184 (2013.01); H01L 23/3121 (2013.01); H01L 23/49582 (2013.01); H01L 25/0655 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68377 (2013.01); H01L 2224/24051 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/24225 (2013.01); H01L 2224/24226 (2013.01); H01L 2224/24998 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/82001 (2013.01); H01L 2224/82039 (2013.01); H01L 2224/82101 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06551 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/0102 (2013.01); H01L 2924/0103 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01012 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01051 (2013.01); H01L 2924/01056 (2013.01); H01L 2924/01075 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H05K 3/284 (2013.01); H05K 3/4644 (2013.01); H05K 2201/10636 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/0264 (2013.01); H05K 2203/0769 (2013.01); H05K 2203/1469 (2013.01);
Abstract

A wiring method is provided in which an insulating layer is formed on a surface of a semiconductor deviceof which a plurality of connecting terminals are exposed, a resin film is formed on a surface of the insulating layer, a groove of a depth equal to or exceeding a thickness of the resin film is formed from a surface side of the resin film so that the groove passes in a vicinity of connecting terminals that are to be connected, and furthermore communicating holes which reach the connecting terminals to be connected from this portion that groove passes in the vicinity thereof are formed.

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