The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Dec. 29, 2010
Applicants:

Hee-min Shin, Cheongju-si, KR;

Cheol-ho Joh, Seoul, KR;

Eun-hye DO, Suwon-si, KR;

Ji-eun Kim, Suwon-si, KR;

Kyu-won Lee, Seoul, KR;

Inventors:

Hee-Min Shin, Cheongju-si, KR;

Cheol-Ho Joh, Seoul, KR;

Eun-Hye Do, Suwon-si, KR;

Ji-Eun Kim, Suwon-si, KR;

Kyu-Won Lee, Seoul, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/3121 (2013.01); H01L 24/18 (2013.01); H01L 24/19 (2013.01); H01L 25/50 (2013.01); H01L 23/5389 (2013.01); H01L 2224/73267 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/01029 (2013.01);
Abstract

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.


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