The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2015
Filed:
Mar. 11, 2014
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventor:
Tae-Sik Na, Seoul, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 5/14 (2006.01); G11C 8/00 (2006.01); G11C 8/16 (2006.01); G11C 11/4076 (2006.01); G11C 5/04 (2006.01); G11C 7/22 (2006.01); G11C 11/4074 (2006.01); G11C 8/18 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 5/04 (2013.01); G11C 7/222 (2013.01); G11C 8/18 (2013.01); G11C 11/4074 (2013.01); G11C 2207/2227 (2013.01); G11C 2207/2272 (2013.01);
Abstract
An operating method of a delay locked loop (DLL) circuit for a semiconductor memory device is disclosed. The DLL circuit may include a plurality of sub-circuits. The method may include calculating an additive latency value based on predetermined parameters, and controlling a set of the plurality of sub-circuits of the DLL circuit to be maintained in a turn-off state based on the calculated additive latency value, during a period of time after the semiconductor device receives an operation command in a power saving mode.