The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Sep. 14, 2012
Applicants:

Seul-ki OH, Gyeonggi-do, KR;

Jun-hyuk Lee, Gyeonggi-do, KR;

Inventors:

Seul-Ki Oh, Gyeonggi-do, KR;

Jun-Hyuk Lee, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0425 (2013.01); G11C 5/02 (2013.01); G11C 5/06 (2013.01); G11C 16/04 (2013.01); G11C 16/0483 (2013.01); H01L 27/11582 (2013.01);
Abstract

A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.


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