The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2015
Filed:
Jul. 24, 2014
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventor:
Jin Hee Cho, Icheon-si, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 8/12 (2006.01); G11C 8/06 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 7/20 (2006.01); G11C 29/12 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 8/12 (2013.01); G11C 5/066 (2013.01); G11C 7/109 (2013.01); G11C 7/1051 (2013.01); G11C 7/1066 (2013.01); G11C 7/20 (2013.01); G11C 7/22 (2013.01); G11C 8/06 (2013.01); G11C 29/1201 (2013.01);
Abstract
A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer configured to buffer the external control signal in response to the buffer control signal and output an internal control signal; and an input buffer control unit configured to generate the buffer control signal in response to an external command.