The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Feb. 14, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Myung-Hee Sung, Hwaseong-Si, KR;

Chang-Woo Ko, Seoul, KR;

Jea-Eun Lee, Seoul, KR;

Young-Ho Lee, Seongnam-Si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 5/04 (2006.01); G11C 7/02 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G11C 5/04 (2013.01); G11C 7/02 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/222 (2013.01); G11C 7/225 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01);
Abstract

A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes.


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