The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Nov. 26, 2013
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Kenta Yasufuku, Kanagawa, JP;

Shigeaki Iwasa, Kanagawa, JP;

Yasuhiko Kurosawa, Kanagawa, JP;

Hiroo Hayashi, Kanagawa, JP;

Seiji Maeda, Kanagawa, JP;

Mitsuo Saito, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 12/10 (2006.01); G06F 12/08 (2006.01); G06F 12/12 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1063 (2013.01); G06F 12/0831 (2013.01); G06F 12/1027 (2013.01); G06F 12/1054 (2013.01); G06F 12/12 (2013.01); G06F 12/1081 (2013.01); Y02B 60/1225 (2013.01);
Abstract

An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.


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