The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Nov. 09, 2012
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

James M. Simkins, Park City, UT (US);

Wayne E. Wennekamp, San Jose, CA (US);

John M. Thendean, Pleasanton, CA (US);

Adam Elkins, San Jose, CA (US);

Richard L. Walke, Edinburgh, GB;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/57 (2006.01);
U.S. Cl.
CPC ...
G06F 7/57 (2013.01);
Abstract

An apparatus is disclosed. This apparatus includes a digital signal processing ('DSP') block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit ('ALU') block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.


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