Information processor and control method of the same

Abstract

Disclosed herein is an information processor including: a processing section adapted to perform a predetermined process on a data signal output in synchronism with one of positive and negative edges of a clock signal and output an execution result thereof; a holding section adapted to hold the execution result in synchronism with the other of the positive and negative edges; a timing determination section adapted to determine whether a grace period lasting until the execution result is held by the holding section meets a setup time of the holding section; a clock control section adapted, if it is determined that the grace period does not meet the setup time, to control at least the timing of either the positive or negative edge in such a manner that the grace period meets the setup time; and a clock generation section adapted to generate the clock signal according to the controlled timing.