The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Jan. 14, 2013
Applicant:

Silergy Technology, Sunnyvale, CA (US);

Inventor:

Budong You, Hangzhou, CN;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H05K 3/34 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/341 (2013.01); Y10T 29/49144 (2015.01); H01L 23/3107 (2013.01); H01L 23/49548 (2013.01); H01L 23/49562 (2013.01); H01L 23/49572 (2013.01); H01L 24/16 (2013.01); H01L 2224/16245 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/14 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/10253 (2013.01); H01L 24/17 (2013.01);
Abstract

Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame.


Find Patent Forward Citations

Loading…