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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9077997 B1

PDFFull Text
Date of Patent:
Jul. 07, 2015

Filed:

Jan. 22, 2004

Graphics display system with unified memory architecture

Applicants:

Alexander G. Macinnis, Los Altos, CA (US);

Chengfuh Jeffrey Tang, Satatoga, CA (US);

Xiaodong Xie, San Jose, CA (US);

James T. Patterson, Saratoga, CA (US);

Greg A. Kranawetter, San Jose, CA (US);

Inventors:

Alexander G. MacInnis, Los Altos, CA (US);

Chengfuh Jeffrey Tang, Satatoga, CA (US);

Xiaodong Xie, San Jose, CA (US);

James T. Patterson, Saratoga, CA (US);

Greg A. Kranawetter, San Jose, CA (US);

Assignee:

BROADCOM CORPORATION, Irvine, CA (US);

Attorney:

Foley & Lardner LLP

Primary Examiner:

Henry Tsai

Assistant Examiner:

Aurangzeb Hassan

Int. Cl.
CPC ...
G06F 3/00 (2006.01); H04N 19/436 (2014.01); G06T 9/00 (2006.01); G09G 5/00 (2006.01); G09G 5/06 (2006.01); G09G 5/12 (2006.01); G09G 5/14 (2006.01); G09G 5/28 (2006.01); G09G 5/34 (2006.01); G09G 5/36 (2006.01); H04N 5/04 (2006.01); H04N 5/14 (2006.01); H04N 5/445 (2011.01); H04N 5/45 (2011.01); H04N 7/01 (2006.01); H04N 9/45 (2006.01); H04N 9/64 (2006.01); H04N 21/422 (2011.01); H04N 21/43 (2011.01); H04N 21/426 (2011.01); H04N 21/431 (2011.01); H04N 21/434 (2011.01); H04N 21/4402 (2011.01); H04N 21/443 (2011.01); H04N 21/47 (2011.01); H04N 19/61 (2014.01); H04N 19/44 (2014.01); H04N 19/42 (2014.01); H04N 19/423 (2014.01); H04N 19/59 (2014.01); G09G 5/02 (2006.01); H04N 5/12 (2006.01); H04N 5/44 (2011.01); H04N 5/46 (2006.01); H04N 11/14 (2006.01); H04N 11/20 (2006.01);
U.S. Cl.
CPC ...
H04N 19/436 (2013.01); G06T 9/00 (2013.01); G06T 9/007 (2013.01); G09G 5/001 (2013.01); G09G 5/02 (2013.01); G09G 5/024 (2013.01); G09G 5/026 (2013.01); G09G 5/06 (2013.01); G09G 5/12 (2013.01); G09G 5/14 (2013.01); G09G 5/28 (2013.01); G09G 5/346 (2013.01); G09G 5/36 (2013.01); G09G 5/363 (2013.01); G09G 2310/0224 (2013.01); G09G 2320/0247 (2013.01); G09G 2340/02 (2013.01); G09G 2340/0407 (2013.01); G09G 2340/10 (2013.01); G09G 2340/125 (2013.01); G09G 2360/02 (2013.01); G09G 2360/121 (2013.01); G09G 2360/125 (2013.01); G09G 2360/126 (2013.01); G09G 2360/128 (2013.01); H04N 5/04 (2013.01); H04N 5/126 (2013.01); H04N 5/14 (2013.01); H04N 5/4401 (2013.01); H04N 5/44504 (2013.01); H04N 5/44508 (2013.01); H04N 5/44591 (2013.01); H04N 5/45 (2013.01); H04N 5/46 (2013.01); H04N 7/0122 (2013.01); H04N 7/0135 (2013.01); H04N 9/45 (2013.01); H04N 9/641 (2013.01); H04N 9/642 (2013.01); H04N 11/143 (2013.01); H04N 11/20 (2013.01); H04N 21/42204 (2013.01); H04N 21/4305 (2013.01); H04N 21/42653 (2013.01); H04N 21/4316 (2013.01); H04N 21/434 (2013.01); H04N 21/440263 (2013.01); H04N 21/4438 (2013.01); H04N 21/47 (2013.01); H04N 19/61 (2014.11); H04N 19/44 (2014.11); H04N 19/42 (2014.11); H04N 19/423 (2014.11); H04N 19/59 (2014.11);
Abstract

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

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