The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Aug. 26, 2011
Applicants:

Osamu Sasaki, Osaka, JP;

Yuhichiroh Murakami, Osaka, JP;

Yasushi Sasaki, Osaka, JP;

Etsuo Yamamoto, Osaka, JP;

Inventors:

Osamu Sasaki, Osaka, JP;

Yuhichiroh Murakami, Osaka, JP;

Yasushi Sasaki, Osaka, JP;

Etsuo Yamamoto, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/18 (2006.01); H01L 33/00 (2010.01); H01L 21/02 (2006.01); H01L 49/02 (2006.01); G09G 3/36 (2006.01); H01L 27/04 (2006.01); H01L 33/08 (2010.01); H01L 27/12 (2006.01); G02F 1/1345 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 28/40 (2013.01); G02F 1/13454 (2013.01); G02F 1/136277 (2013.01); G09G 3/3648 (2013.01); G09G 2310/0286 (2013.01); H01L 27/04 (2013.01); H01L 33/08 (2013.01); H01L 27/1255 (2013.01); G09G 3/3611 (2013.01);
Abstract

A semiconductor device () provided with at least a plurality of transistors and bootstrap capacitors (Caand Cb), the semiconductor device () includes: a semiconductor layer () made of the same material as a channel layer of each of the transistors; a capacitor electrode () formed in an upper layer of the semiconductor layer (); and a clock signal line () formed in an upper layer of the capacitor electrode (), the capacitor electrode () being connected to a gate electrode of each of the transistors, the clock signal line () being supplied with a clock signal (CK) from outside the semiconductor device (), the capacitors (Caand Cb) each being formed in an overlap section where the semiconductor layer (), the gate insulating film () and the capacitor electrode () overlap one another, the overlap section and the clock signal line () overlapping each other when viewed from above.


Find Patent Forward Citations

Loading…