The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Oct. 16, 2014
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventor:

Tsung-Hsiung Lee, Taoyuan County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 29/10 (2006.01); H01L 21/225 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1045 (2013.01); H01L 21/2257 (2013.01); H01L 29/66727 (2013.01); H01L 29/7802 (2013.01); H01L 29/04 (2013.01); H01L 29/0634 (2013.01); H01L 29/1095 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/02634 (2013.01); H01L 21/26513 (2013.01); H01L 29/66712 (2013.01);
Abstract

A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.


Find Patent Forward Citations

Lee, Tsung-Hsiung. (2015). Method for fabricating semiconductor device with super junction structure (U.S. Patent No. 9076677). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9076677

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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