The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Sep. 15, 2011
Applicants:

Oren Agam, Ya'acov, IL;

Avidan Akerib, Tel-Aviv, IL;

Eli Ehrman, Beit Shemesh, IL;

Moshe Meyassed, Kadima, IL;

Inventors:

Oren Agam, Ya'acov, IL;

Avidan Akerib, Tel-Aviv, IL;

Eli Ehrman, Beit Shemesh, IL;

Moshe Meyassed, Kadima, IL;

Assignee:

MIKAMONU GROUP LTD., Zahala Tel Aviv, IL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 15/00 (2006.01); G11C 15/04 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); G11C 7/10 (2006.01); G11C 11/403 (2006.01);
U.S. Cl.
CPC ...
G11C 15/043 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 7/1006 (2013.01); G11C 11/403 (2013.01);
Abstract

A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.


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