Synchronous nonvolatile memory device and memory system supporting consecutive division addressing dram protocol

Abstract

A nonvolatile memory device and system having a nonvolatile memory device accessible with a DRAM protocol for generating a first command signal and a second command signal based on a row address strobe signal and a column address strobe signal and storing an n-bit row address signal based on the first command signal, an n-bit column address signal based on the second command signal, and decoding the n-bit row address signal and the n-bit column address signal to synchronously provide a row selection signal and a column selection signal to a memory cell array.