The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Sep. 28, 2012
Applicant:

Wanfang Tsai, Mountain View, CA (US);

Inventor:

Wanfang Tsai, Mountain View, CA (US);

Assignee:

SanDisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 19/00 (2006.01); G11C 16/08 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1036 (2013.01); G11C 2207/107 (2013.01); G11C 19/00 (2013.01); G11C 2211/5642 (2013.01); G11C 16/08 (2013.01); G11C 29/82 (2013.01);
Abstract

A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to 1 conversion, data is received from an (N×m)-wide parallel data bus in an N by m wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent.


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