The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Mar. 06, 2014
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventor:

Hiroomi Nakajima, Mie-ken, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01Q 1/22 (2006.01); H01L 23/522 (2006.01); H01L 27/06 (2006.01); H01L 27/115 (2006.01); H01L 49/02 (2006.01); H01L 29/792 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); H01Q 1/2283 (2013.01); G11C 16/0483 (2013.01); H01L 23/5227 (2013.01); H01L 27/0629 (2013.01); H01L 27/11531 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); H01L 28/10 (2013.01); H01L 29/7926 (2013.01);
Abstract

According to one embodiment, a non-volatile memory device includes a memory cell array and a coil provided closely to the memory cell array. The memory cell array includes memory cells provided above an underlying layer, and a first interconnection. The memory cells are aligned in a first direction perpendicular to the underlying layer. The first interconnection extends in a second direction perpendicular to the first direction. The coil includes a winding including a second interconnection extending in the second direction and sharing a central axis with the first interconnection, a first plug extending in the first direction and connected to the second interconnection, a third interconnection electrically connected to another end of the first plug and extending in a direction parallel to the underlying layer, and a second plug having one end electrically connected to the third interconnection, and extending in a direction opposite to the first direction.


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