The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2015
Filed:
May. 11, 2012
Shinya Tanaka, Osaka, JP;
Shinya Tanaka, Osaka, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
The present invention is directed to suppress dullness of a scanning signal in a scanning signal line drive circuit. A bistable circuit is provided with an input terminal () for receiving a first clock signal (CK), an input terminal () for receiving a control signal (CT), an input terminal () for receiving a level down signal (LD), an output terminal (), a thin film transistor (T), and a thin film transistor (TA). The thin film transistor (T) has a gate terminal connected to a first node (N), a drain terminal connected to the input terminal (), and a source terminal connected to the output terminal (). The thin film transistor (TA) has a gate terminal connected to the input terminal (), a drain terminal connected to the first node (N), and a source terminal connected to the input terminal (). The potential of the control signal (CT) becomes the high level in a control period as a period except for the first one horizontal scanning period in a vertical blanking period. The level down signal (LD) is a potential lower than DC power supply potential (Vss).