The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Nov. 09, 2012
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Subodh Kumar, San Jose, CA (US);

James M. Simkins, Park City, UT (US);

Thomas H. Strader, Corona, CA (US);

Matthew H. Klein, Redwood City, CA (US);

James E. Ogden, Tracy, CA (US);

Uma Durairajan, Sunnyvale, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G06F 13/42 (2006.01); H03K 19/177 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4234 (2013.01); G11C 7/1006 (2013.01); H03K 19/17732 (2013.01); H03K 19/1776 (2013.01); G11C 7/1039 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 2207/104 (2013.01); G11C 16/26 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.


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