The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2015
Filed:
Oct. 23, 2012
Axis Semiconductor, Inc., Boxborough, MA (US);
Xiaolin Wang, Concord, MA (US);
Qian Wu, Redwood City, CA (US);
Ben Marshall, Stow, MA (US);
John Eppling, Acton, MA (US);
Jie Sun, Sudbury, MA (US);
RS STATA LLC, Waltham, MA (US);
Abstract
A multi-core processor includes a tree-like structure having a plurality of computing cores arranged in hierarchical levels, the cores all having the same logical architecture. Each core can include computing, interconnecting, and/or storage elements. The functionality of an individual element can be supplied by an entire core in a lower level. A method for programming the processor includes hierarchically decomposing an application into interconnected sub-functions, mapping the sub-functions onto groups of cores at appropriate levels of the processor, and interconnecting the mapped sub-functions so as to hierarchically compose the complete application. Sub-functions can be sequential, concurrent, and/or pipelined. Interconnections can be static or dynamically switchable under program control. Interconnect elements can also be used to implement flow control as needed in pipelined operations to maintain data coherency. The decomposing and mapping process can be iterated on sub-functions so as to optimize load balancing, software performance, and hardware efficiency.