The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Jan. 10, 2014
Applicant:

Uniquify, Incorporated, San Jose, CA (US);

Inventors:

Jung Lee, Santa Clara, CA (US);

Mahesh Goplan, Santa Clara, CA (US);

Assignee:

UNIQUIFY, INCORPORATED, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 1/12 (2006.01); G06F 12/06 (2006.01); G11C 7/22 (2006.01); G06F 1/04 (2006.01); G06F 3/06 (2006.01); G06F 1/14 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 13/1689 (2013.01); G06F 13/4243 (2013.01); G11C 29/02 (2013.01); G11C 29/028 (2013.01); G11C 29/50 (2013.01); G11C 29/50012 (2013.01); G06F 1/12 (2013.01); G06F 12/0646 (2013.01); G11C 7/222 (2013.01); G06F 1/04 (2013.01); G06F 3/0619 (2013.01); G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 1/14 (2013.01);
Abstract

A method for calibrating a memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface.


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