The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Jun. 30, 2011
Applicants:

Zongliang Huo, Beijing, CN;

Ming Liu, Beijing, CN;

Inventors:

Zongliang Huo, Beijing, CN;

Ming Liu, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 45/00 (2006.01); H01L 27/06 (2006.01); H01L 27/10 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1206 (2013.01); H01L 27/0688 (2013.01); H01L 27/101 (2013.01); H01L 45/04 (2013.01); H01L 45/14 (2013.01); H01L 45/16 (2013.01); H01L 27/2436 (2013.01); H01L 27/249 (2013.01);
Abstract

The present disclosure provides a method for manufacturing a three-dimensional semiconductor memory device. In the method, a storage array is divided into a plurality of storage sub-arrays. As a result, a respective via of each storage sub-array can be etched respectively, which is different from the prior art, where a via for a bottom electrode of a plurality of layers of resistive cells is etched at one time. The vias are filled with metal so that storage sub-arrays are connected with each other. The method for manufacturing the three-dimensional semiconductor memory device according to the present disclosure can substantially reduce process complexity and difficulty of etching process in high-density integration, and also improve a number of layers of the resistive cells integrated in the storage array.


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