The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Mar. 26, 2014
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Rudy Octavius Sihombing, Medan, ID;

Shang-Hui Tu, Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device layout structure is provided. The semiconductor device layout structure includes an active region having a first conductivity type over a semiconductor substrate. The active region is provided with semiconductor devices formed thereon. A first super junction layout unit in the active region includes a first trench. A first doped region having a first conductivity type is formed surrounding the first trench. A second trench is formed surrounding the first doped region. A second doped region having a second conductivity type is formed surrounding the second trench. The first trench is laterally separated from the second trench through the first doped region and the second doped region in a plan view.


Find Patent Forward Citations

Sihombing, Rudy. (2015). Semiconductor device layout structure (U.S. Patent No. 9070763). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9070763

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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