The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2015
Filed:
Oct. 29, 2007
Applicants:
Shunpei Yamazaki, Tokyo, JP;
Hisashi Ohtani, Kanagawa, JP;
Inventors:
Shunpei Yamazaki, Tokyo, JP;
Hisashi Ohtani, Kanagawa, JP;
Assignee:
Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/00 (2006.01); H01L 31/036 (2006.01); H01L 31/112 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 27/14 (2006.01); H01L 29/04 (2006.01); H01L 29/15 (2006.01); H01L 31/062 (2012.01); H01L 31/113 (2006.01); H01L 27/12 (2006.01); H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1266 (2013.01); H01L 21/76243 (2013.01); H01L 21/76254 (2013.01); H01L 21/76256 (2013.01); H01L 27/1203 (2013.01); H01L 27/1214 (2013.01); H01L 29/045 (2013.01); H01L 29/66772 (2013.01); H01L 29/78603 (2013.01); Y10S 438/977 (2013.01); Y10S 438/973 (2013.01);
Abstract
A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.