The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Mar. 29, 2013
Applicant:

National Chiao Tung University, Hsinchu, TW;

Inventors:

Chia-Ching Chu, Taichung, TW;

Yi-Min Lin, Taipei, TW;

Chi-Heng Yang, New Taipei, TW;

Hsie-Chia Chang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G06F 11/10 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
G06F 11/10 (2013.01); H03M 13/152 (2013.01); H03M 13/1525 (2013.01); H03M 13/1545 (2013.01); H03M 13/611 (2013.01); H03M 13/617 (2013.01); H03M 13/6561 (2013.01);
Abstract

A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.


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