The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Mar. 01, 2013
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Gus Yeung, Austin, TX (US);

Bo Zheng, Cupertino, CA (US);

Frank Guo, Danville, CA (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 12/00 (2006.01); G11C 5/14 (2006.01); G11C 11/417 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 12/00 (2013.01); G11C 5/147 (2013.01); G11C 7/1039 (2013.01); G11C 7/1057 (2013.01); G11C 7/106 (2013.01); G11C 7/1084 (2013.01); G11C 7/1087 (2013.01); G11C 11/417 (2013.01);
Abstract

An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.


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