The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Aug. 02, 2012
Applicants:

Jeffrey A. Pangborn, Saratoga, CA (US);

Gregg A. Bouchard, Georgetown, TX (US);

Rajan Goyal, Saratoga, CA (US);

Najeeb I. Ansari, San Jose, CA (US);

Ahmed Shahid, San Jose, CA (US);

Inventors:

Jeffrey A. Pangborn, Saratoga, CA (US);

Gregg A. Bouchard, Georgetown, TX (US);

Rajan Goyal, Saratoga, CA (US);

Najeeb I. Ansari, San Jose, CA (US);

Ahmed Shahid, San Jose, CA (US);

Assignee:

Cavium, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); H04L 29/06 (2006.01); G06F 13/16 (2006.01); G06F 12/08 (2006.01); G06F 12/02 (2006.01); G06F 12/04 (2006.01); G06F 12/06 (2006.01); G06N 5/02 (2006.01); H04L 12/26 (2006.01); H04L 12/747 (2013.01); H04L 12/851 (2013.01); H04L 12/801 (2013.01); H04L 12/741 (2013.01); G06F 9/50 (2006.01); H04L 29/08 (2006.01); G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
H04L 69/22 (2013.01); G06F 13/16 (2013.01); G06F 12/0802 (2013.01); G06F 12/0207 (2013.01); G06F 12/04 (2013.01); G06F 12/0623 (2013.01); G06F 13/1642 (2013.01); G06F 12/00 (2013.01); G06F 12/06 (2013.01); G06N 5/02 (2013.01); H04L 43/18 (2013.01); H04L 63/0227 (2013.01); H04L 45/742 (2013.01); H04L 47/2441 (2013.01); H04L 47/39 (2013.01); H04L 45/745 (2013.01); G06F 9/5027 (2013.01); H04L 67/10 (2013.01); G06F 9/46 (2013.01); Y02B 60/142 (2013.01); G06F 9/5016 (2013.01);
Abstract

A processor with on-chip memory including a plurality of physical memory banks is disclosed. The processor includes a method, and corresponding apparatus, of enabling multi-access to the plurality of physical memory banks. The method comprises selecting a subset of multiple access requests to be executed in at least one clock cycle over at least one of a number of access ports connected to the plurality of physical memory banks, the selected subset of access requests addressed to different physical memory banks, among the plurality of memory banks, and scheduling the selected subset of access requests, each over a separate access port.


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