The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2015
Filed:
Oct. 08, 2012
Koninklijke Philips N.v., Eindhoven, NL;
KONINKLIJKE PHILIPS N.V., Eindhoven, NL;
Abstract
The present invention relates to a method of assembling VCSEL chips () on a sub-mount (). A de-wetting layer () is deposited on a connecting side of the VCSEL chips () which is to be connected to the sub-mount (). A further de-wetting layer () is deposited on a connecting side of the sub-mount () which is to be connected to the VCSEL chips (). The de-wetting layers () are deposited with a patterned design or are patterned after depositing to define connecting areas () on the sub-mount () and the VCSEL chips (). A solder () is applied to the connecting areas () of at least one of the two connecting sides. The VCSEL chips () are placed on the sub-mount () and soldered to the sub-mount () to electrically and mechanically connect the VCSEL chips () and the sub-mount (). With the proposed method a high alignment accuracy of the VCSEL chips () on the sub-mount () is achieved without time consuming measures.