The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2015
Filed:
Apr. 20, 2011
Applicants:
Norihisa Asano, Osaka, JP;
Kazuyoshi Imae, Osaka, JP;
Inventors:
Norihisa Asano, Osaka, JP;
Kazuyoshi Imae, Osaka, JP;
Assignee:
SHARP KABUSHIKI KAISHA, Osaka, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/522 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/522 (2013.01); G02F 1/1368 (2013.01); H01L 27/12 (2013.01); H01L 29/78606 (2013.01); H01L 21/76838 (2013.01); H01L 27/124 (2013.01); H01L 27/1248 (2013.01); H01L 2924/0002 (2013.01);
Abstract
Disclosed is a semiconductor device provided with: lower-layer wiring formed on a substrate, an interlayer insulating film covering the lower-layer wiring, and a first upper-layer wiring line () and a second upper-layer wiring line () arranged on the interlayer insulating film and intersecting with the lower-layer wiring, and a level-difference adjustment protrusion is provided between the first upper-layer wiring line () and the second upper-layer wiring line () adjacent to a side section of the lower-layer wiring.