The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Mar. 18, 2013
Applicant:

Robert William Musk, Kingsbridge, GB;

Inventor:

Robert William Musk, Kingsbridge, GB;

Assignee:

EFFECT PHOTONICS B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); G02B 6/12 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4985 (2013.01); H01L 24/14 (2013.01); H01L 23/3142 (2013.01); G02B 6/12 (2013.01); H01L 2224/13144 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/10335 (2013.01); H01L 2924/14 (2013.01);
Abstract

An assembly () includes a substrate () that is provided with at least one electrical contact (), a flexible printed circuit membrane () including an electrically insulating film () and an electrically conducting layer () that is at least partially covering the insulating film (). The conducting layer () is at least locally accessible from outside of the membrane (). A connection element () is provided for electrically connecting the at least one electrical contact () and the conducting layer () at a position where the conducting layer () is accessible, to form an electrical connection between the substrate () and the membrane (). A chip package () includes a housing () having at least one electrically conducting terminal, and an assembly () as mentioned. The flexible printed circuit membrane () is arranged for electrically connecting the substrate and the at least one terminal of the housing ().


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