The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Jun. 04, 2007
Applicant:

Teruyuki Fujii, Kanagawa, JP;

Inventor:

Teruyuki Fujii, Kanagawa, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 51/40 (2006.01); H01L 27/32 (2006.01); H01L 29/45 (2006.01); H01L 51/56 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3246 (2013.01); H01L 27/3283 (2013.01); H01L 29/458 (2013.01); H01L 51/56 (2013.01); H01L 27/1248 (2013.01);
Abstract

An object is to provide a semiconductor device with excellent reproducibility which is manufactured at low cost. A method for manufacturing a semiconductor device includes steps of forming a first electrode over a substrate; forming an insulating layer over the substrate and the first electrode; pressing a mold against the insulating layer to form an opening in the insulating layer; separating the mold from the insulating layer in which opening is formed; hardening the insulating layer in which the opening is formed to form a partition wall; forming a light-emitting layer over the first electrode and the partition wall; and forming a second electrode over the light-emitting layer. As a method for forming the partition wall, nano-imprinting is used. An insulating layer contains polysilane. The partition wall formed of a silicon oxide film is formed by UV light irradiation and heating.


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