The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2015
Filed:
Sep. 28, 2012
Ngk Insulators, Ltd., Nagoya, JP;
Shinsuke Yano, Nagoya, JP;
Takami Hirai, Toyota, JP;
Tsutomu Nanataki, Toyoake, JP;
Hirofumi Yamaguchi, Komaki, JP;
NGK Insulators, Ltd., Nagoya, JP;
Abstract
Problems, such as increase in the electrical resistance in the junction(s) of the terminal(s) of a power semiconductor element and the electrode(s) of a peripheral circuit and decrease in the dielectric strength voltage between adjacent junctions, resulting from the insufficient alignment of the power semiconductor element terminal(s) and the the peripheral circuit electrode(s), in the high-capacity module which is intended to attain reduction in size and weight, reduction in surge, and reduction in loss by lamination of the peripheral circuit onto the power circuit, should be reduced. By preparing level difference(s) in the surface of the peripheral circuit board to more accurately align the peripheral circuit board electrode(s) and the power semiconductor element terminal(s) by contact of the level difference(s) and the lateral face(s) of the power semiconductor element at the time of lamination of the power circuit and the peripheral circuit, the above-mentioned problems can be reduced.