The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Jul. 03, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Wilfried Ernst-August Haensch, Somers, NY (US);

Zihong Liu, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/12 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/16 (2006.01); H01L 21/268 (2006.01); H01L 21/283 (2006.01); H01L 21/308 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/43 (2006.01);
U.S. Cl.
CPC ...
H01L 29/122 (2013.01); H01L 29/42364 (2013.01); H01L 29/42376 (2013.01); H01L 29/66431 (2013.01); H01L 29/7781 (2013.01); H01L 29/1606 (2013.01); H01L 21/2686 (2013.01); H01L 21/283 (2013.01); H01L 21/308 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/66515 (2013.01); H01L 29/66742 (2013.01); H01L 29/78684 (2013.01); H01L 29/0669 (2013.01); H01L 29/43 (2013.01);
Abstract

Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.


Find Patent Forward Citations

Haensch, Wilfried Ernst-August. (2015). Graphene and nanotube/nanowire transistor with a self-aligned gate structure on transparent substrates and method of making same (U.S. Patent No. 9064748). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9064748

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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