The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Nov. 08, 2012
Applicant:

Skyworks Solutions, Inc., Woburn, MA (US);

Inventor:

Jonathan Christian Crandall, Marion, IA (US);

Assignee:

Skyworks Solutions, Inc., Woburn, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/28 (2006.01); H01L 29/74 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01); H04B 1/38 (2015.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1211 (2013.01); H01L 29/78 (2013.01); H04B 1/38 (2013.01); H01L 29/41758 (2013.01); H01L 29/66568 (2013.01); H01L 29/0692 (2013.01);
Abstract

Disclosed are devices and methods related to field-effect transistor (FET) structures configured to provide reduced per-area values of resistance in the linear operating region (Rds-on). Typical FET devices such as silicon-on-insulator (SOI) device require larger device sizes to desirably lower the Rds-on values. However, such increases in size result in undesirably larger die sizes. Disclosed are various examples of shapes of source, drain, and corresponding gate that yield reduced Rds-on values without having to increase the device size. In some implementations, such FET devices can be utilized in high power radio-frequency (RF) switching applications.


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