The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Feb. 13, 2013
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Nam Kyun Park, Seoul, KR;

Gap Sok Do, Seoul, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01); G11C 17/16 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0004 (2013.01); H01L 45/04 (2013.01); H01L 45/16 (2013.01); G11C 11/16 (2013.01); G11C 17/16 (2013.01); H01L 45/06 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/142 (2013.01); H01L 45/143 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); H01L 45/1683 (2013.01); H01L 27/2436 (2013.01); H01L 27/2454 (2013.01); H01L 27/2463 (2013.01); H01L 27/2481 (2013.01); G11C 13/0011 (2013.01); G11C 13/0016 (2013.01);
Abstract

Provided are a variable resistive memory device, and methods of fabricating and driving the same. The variable resistive memory device includes a plurality of memory cells arranged in a first direction and in a second direction different from the first direction, each of the plurality of memory cells comprising a variable resistor and a selection device serially connected to the variable resistor. A common wiring is electrically connected to first ends of the plurality of memory cells to apply a common reference voltage. Each wiring line of a plurality of wiring lines is electrically connected to second ends of the plurality of memory cells arranged n the plurality of rows oriented in the first direction. A plurality of selection lines are respectively connected to the selection devices of the plurality of memory cells to select any one of the plurality of memory cells via the plurality of wiring lines.


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