The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Apr. 02, 2012
Applicant:

Betina Hold, El Dorado Hills, CA (US);

Inventor:

Betina Hold, El Dorado Hills, CA (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/02 (2006.01); G11C 11/00 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/00 (2013.01); G11C 7/1006 (2013.01); G11C 7/1078 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01); G11C 7/227 (2013.01);
Abstract

A memory device includes an array of memory cells arranged into a plurality of rows and columns and having a plurality of word lines and a plurality of bit lines passing through the array. The memory cells in each row are activated via a word line signal on the corresponding word line, and the memory cells in each column are coupled to an associated bit line pair via which data is written into an activated memory cell of the column during a write operation and data is read from the activated memory cell of the column during a read operation. A dummy column of dummy memory cells is provided and includes a plurality of loading dummy memory cells for providing a load to the at least one dummy bit line, and at least one write timing dummy memory cell coupled to a dummy word line.


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