The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Nov. 14, 2011
Applicants:

Joerg Kayser, Waldenbuch, DE;

Helmut Kohler, Moensheim, DE;

Norbert Schumacher, Forchtenberg, DE;

Inventors:

Joerg Kayser, Waldenbuch, DE;

Helmut Kohler, Moensheim, DE;

Norbert Schumacher, Forchtenberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01); G06F 17/5081 (2013.01);
Abstract

According to one aspect of the present disclosure, a method and technique for identifying odd nets in a hierarchical electronic circuit design is disclosed. The method includes: receiving a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design; modifying an architecture section of VHDL code of each endpoint component of the VHDL model to connect each input/output (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code; executing a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components; and extracting an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.


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