The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2015
Filed:
Feb. 07, 2011
Applicants:
Hiroshi Ikeda, Yokohama, JP;
Hidetoshi Matsuoka, Yokohama, JP;
Inventors:
Hiroshi Ikeda, Yokohama, JP;
Hidetoshi Matsuoka, Yokohama, JP;
Assignee:
FUJITSU SEMICONDUCTOR LIMITED, Yokohama, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01); G11C 29/50 (2013.01); G11C 29/50004 (2013.01); G11C 29/50012 (2013.01); G11C 2029/5002 (2013.01); G11C 2029/5004 (2013.01); G11C 2029/5006 (2013.01); G06F 17/5045 (2013.01); G06F 2217/08 (2013.01); G06F 2217/10 (2013.01); G06F 17/5009 (2013.01);
Abstract
Disclosed is a simulation method for simulating an operation of a device. The simulation method includes specifying, by a computer, a boundary between a non-defective status and a defective status of a product in design space with a design parameter as an origin. The boundary is specified according to a search using a search indicator defined based on an operating state different from an operating state of a determination indicator that determines the non-defective status and the defective status of the operation.