The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Jan. 05, 2012
Applicants:

Edgar R. Cordero, Round Rock, TX (US);

Joab D. Henderson, Austin, TX (US);

Divya Kumar, Austin, TX (US);

Jeffrey A. Sabrowski, Leander, TX (US);

Anuwat Saetow, Austin, TX (US);

Inventors:

Edgar R. Cordero, Round Rock, TX (US);

Joab D. Henderson, Austin, TX (US);

Divya Kumar, Austin, TX (US);

Jeffrey A. Sabrowski, Leander, TX (US);

Anuwat Saetow, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/18 (2006.01); G06F 11/16 (2006.01); G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06F 11/20 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1666 (2013.01); G11C 29/76 (2013.01); G06F 11/20 (2013.01); G06F 11/141 (2013.01); G06F 11/1048 (2013.01);
Abstract

A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.


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