The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Aug. 08, 2011
Applicants:

Yoong OH, Gyeonggi-do, KR;

Cheol Ho Choi, Gyeonggi-do, KR;

Inventors:

Yoong Oh, Gyeonggi-do, KR;

Cheol Ho Choi, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/02 (2006.01); H05K 3/10 (2006.01); H05K 3/00 (2006.01); H05K 1/00 (2006.01); H05K 1/03 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4652 (2013.01); Y10T 29/49155 (2015.01); H05K 2203/0733 (2013.01); H05K 2203/1189 (2013.01);
Abstract

A method for manufacturing a multi-layer printed circuit board includes: forming first bumps on one surface of a first copper layer at a predetermined interval; providing, on the first copper layer, an insulating layer through which the first bumps are penetrating; stacking a second copper layer on a top of the insulating layer; forming circuits by patterning the first copper layer and the second copper layer; laminating insulating films on top and bottom surfaces of the insulating layer on which the circuits have been formed; forming second bumps on one surface of a third copper layer and of a fourth copper layer at a predetermined interval; and stacking the third copper layer and fourth copper layer, provided with the second bumps, on the top and bottom surfaces of the insulating films.


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